Design for Testability (DFT), is one of the effective ways to overcome power consumption challenges and huge data volumes in the testing process after production, which has grown dramatically in lower geometry node designs. DFT is becoming a key factor that saves higher design cost, higher power consumption, increasing execution testing time, chip area, pin counts, and other new fault types at small geometries in the testing phase itself.
Our team of highly experienced implementation and Design-for-Test (DFT) engineers use a best in class design flow that uses either Synopsys IC Compiler II or Cadence Innovus Implementation System for physical design, the Mentor Tessent Suite for DFT, and Mentor Calibre for physical verification and sign-off. Our services range from RTL-to-GDSII block-level implementation for mixed signal analog-on-top design to hierarchical digital design in leading edge nodes.
With the ongoing trend of lower technology nodes, there is an increase in system-on-chip variations like size, threshold voltage and wire resistance. Due to these factors, new models and techniques are introduced to high-quality testing.
ASIC design is complex enough at different stages of the design cycle. Telling the customers that the chips have fault when you are already at the production stage is embarrassing and disruptive. It’s a situation that no engineering team wants to be in. In order to overcome this situation, design for test is introduced with a list of techniques:
The semiconductor designs are getting more complex, owing to the need for lower geometries like 28nm, 16nm, 7nm, and beyond, even while the number of I/O pins on the processor increases. As transistor count increases exponentially, which affects the cost involved in enhancing testers, and types of test patterns (more logic gates to be tested) applied in multiple test cycles to achieve high test quality.
To limit the use of number of pin-counts, testers, and reduction in the overall product cost in a more efficient manner, DFT engineers are turning to new testability techniques to apply on a growing number of pin counts, and scan patterns in an efficient manner, such as reduced pin-count testing (RPCT).
Scan Path Insertion is a methodology of linking all registers elements into one long shift register (scan path). This can help to check small parts of design instead of the whole design in one go.
Memory BIST, In the lower technology node, chip memory requires lower area and fast access time. MBIST is a device which is used to check RAMs. It is a comprehensive solution to memory testing errors and self-repair proficiencies.
ATPG is a method of creating test vectors / sequential input patterns to check the design for faults generated within various elements of a circuit.