This is the stage wherein our engineers follow the ASIC design layout requirement and specification to create its structure using EDA tools and proven methodologies. This design structure is going to be verified with the help of HLL programming languages like C++ or System C.
After understanding the design specifications, our engineers partition the entire ASIC into multiple functional blocks (hierarchical modules), while keeping in mind ASIC’s best performance, technical feasibility, and resource allocation in terms of area, power, cost and time. Once all the functional blocks are implemented in the architectural document, our engineers brainstorm ASIC design partitioning by reusing IPs from previous projects and procuring them from other parties.
After, DFT, the physical implementation process is to be followed. In physical design, the first step in RTL-to-GDSII design is floor planning. It is the process of placing blocks in the chip. It includes: block placement, design portioning, pin placement, and power optimization.
Floorplan determines the size of the chip, places the gates and connects them with wires. While connecting, engineers take care of wire length, and functionality which will ensure signals will not interfere with nearby elements. In the end, simulate the final floor plan with post-layout verification process.
A good floor planning exercise should come across and take care of minimizing the total chip area, routing phase and improving signal delays; otherwise, the life of IC and its cost will blow out.
Placement is the process of placing standard cells in row. A poor placement requires larger area and also degrades performance. Various factors, like the timing requirement, the net lengths and hence the connections of cells, power dissipation should be taken care. It removes timing violation.
Then it comes to Clock tree synthesis, which is a process of building the clock tree and meeting the defined timing, area and power requirements. It helps in providing the clock connection to the clock pin of a sequential element in the required time and area, with low power consumption.
In order to avoid high power consumption, increase in delays and a huge number of transitions, certain structures can be used for optimizing CTS structure such as Mesh Structure, H-Tree Structure, X-Tree Structure, Fishbone Structure and Hybrid structure.
With the help of these structures, each flop in the clock tree gets the clock connection. During the optimization, tools insert the buffer to build the CTS structure. Different clock structures will build the clock tree with a minimum buffer insertion and lower power consumption of chips.